LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY huxideng IS     
  PORT (CLK:in STD_LOGIC;
         --Q :out STD_LOGIC_VECTOR(7 DOWNTO 0);
         Q:OUT STD_LOGIC;
         row:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         cnt_qiehuan:OUT INTEGER RANGE 0 TO 2
         ); 
END ENTITY huxideng ; 
ARCHITECTURE a OF huxideng IS
signal clk1k,clk1w,clk_5:std_logic;
signal cnt:std_logic;
signal cnt1,cnt2:integer range 0 to 999;
signal tmp_qiehuan:integer range 0 to 2;

BEGIN
PROCESS(CLK)   ----------1000000hz
 variable count:integer range 0 to 9;
   BEGIN
	IF CLK'EVENT AND CLK='1' THEN
	  if count=9 then clk1w<=not clk1w;
		count:=0;
		else count:=count+1;
    	end if;
end if;
end process;
PROCESS(CLK)   ----------1000hz
 variable count:integer range 0 to 9999;
   BEGIN
	IF CLK'EVENT AND CLK='1' THEN
	  if count=9999 then clk1k<=not clk1k;
		count:=0;
		else count:=count+1;
    	end if;
end if;
end process;
process(clk1k)------------0.5hz
variable count:integer range 0 to 999;
begin
if clk1k'event and clk1k='1' then
	if count=999 then clk_5<=not clk_5;
	count:=0;
	else count:=count+1;
	end if;
end if;
end process;

process(clk_5)
begin
cnt<=clk_5;
end process;

PROCESS(clk_5)
begin 
	if clk_5'event and clk_5='1' then
		if tmp_qiehuan=2 then
			tmp_qiehuan<=0;
		else 
			tmp_qiehuan<=tmp_qiehuan+1;
		end if;
	end if;
end process;
			
process(clk1k)------------PWMjishu
begin
if clk1k'event and clk1k='1' then
	if cnt1=999 then cnt1<=0;
	else cnt1<=cnt1+1;
	end if;
end if;
end process;

process(clk1w)--------------PWMjishu
begin
if clk1w'event and clk1w='1' then
	if cnt2=999 then cnt2<=0;
	else cnt2<=cnt2+1;
	end if;
end if;
end process;

process(clk1w,cnt,cnt1,cnt2)
begin
if clk1w'event and clk1w='1' then
	if cnt='1' then
		--if cnt1>cnt2 then Q<="11110000";
		--else Q<="00000000";
		if cnt1>cnt2 then Q<='1';
		else Q<='0';
		end if;
	end if;
	if cnt='0' then
		if cnt1>cnt2 then Q<='0';
		else Q<='1';
		end if;
	end if;
end if;
end process;
row<="01111111";
cnt_qiehuan<=tmp_qiehuan;
end;